Semiconductor memory test apparatus and method for address generation for defect analysis

ABSTRACT

There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing during interleave operation of a memory device having a burst function between banks. Each of the registers corresponding to DUT banks holds a line address of the corresponding bank. When a start row address of one of the banks is input to the DUT, a line address of the same bank as the start row address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start row address. Furthermore, during burst operation of the bank, it is possible to output the line address to the failure analysis memory together the same row address as the memory device generated by calculating the start row address for each clock cycle.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory testapparatus which tests a memory device such as an SDRAM (synchronousDRAM), and more particularly to a semiconductor memory test apparatuscapable of easily generating an address to be inputted to a failureanalysis memory in a test during an inter-bank interleave operation of amemory device having a plurality of banks, and a failure analysisaddress generator constituting the semiconductor memory test apparatus.

BACKGROUND ART

[0002] A semiconductor memory test apparatus inputs a test patternsignal to a memory device, and compares a response output signal fromthe memory device with an expected value pattern signal. Further, itdetects a mismatch of a comparison result as a failure of the memorycell, and stores failure information (fail data) in a failure analysismemory. In the failure analysis memory, the same address space as thatof the memory device is set, and failure information is stored at thesame address as an address of a failure cell.

[0003] Meanwhile, in recent years, in a memory device such as an SDRAM(synchronous DRAM), an increase in data read/write speed is achieved byan operation in a burst mode. In the burst mode, when only a startaddress (first address) is given, subsequent addresses are sequentiallyautomatically generated.

[0004] Therefore, in a test of the memory device which operates in theburst mode, only the start address is inputted to the memory device. Onthe contrary, not only the start address but also addresses which areautomatically generated in the memory device must be inputted to thefailure analysis memory. Thus, in a conventional semiconductor memorytest apparatus, there are inputted the start address as well asaddresses sequentially obtained by operating the start address in theburst period. As a result, the same address space as that of the memorydevice as a device under test can be set in the failure analysis memory.

[0005] An address generation operation in the conventional semiconductormemory test apparatus will now be described with reference to a timingchart of FIG. 4.

[0006]FIG. 4 shows an example of a timing of address generation whentesting an SDRAM which has a plurality of banks, operates with respectto row addresses in a burst mode and has burst length of “2”.

[0007] (A) in FIG. 4 shows input timings of a command, an address and abank address to a memory device under test (DUT). Furthermore, (B) inFIG. 4 shows generation timings of a row address (Row), a start columnaddress (Col), an increment and a bank address in an address generatorof a test pattern generator (ALPG). Moreover, (C) in FIG. 4 shows inputtimings of a row address (Row) and a column address (Col) as failureanalysis addresses to a failure analysis memory (FM).

[0008] A description will now be given as to generation timings ofaddresses and the like in the test pattern generator indicated by (B) inFIG. 4, input timings of addresses and the like to the memory deviceindicated by (A) in FIG. 4, and input timings of addresses and the liketo the failure analysis memory indicated by (C) in FIG. 4 in thementioned order.

[0009] (1) Generation Timing in Test Pattern Generator

[0010] {circle over (1)} Row Address (X) and Bank Address (N)

[0011] As indicated by (B) in FIG. 4, the address generator continuouslygenerates a bank address (RBK) and a row address (Row) after a clockcycle <1>. Here, as the bank address, “RBK (0)” specifying a 0th bank ofthe SDRAM is generated. Additionally, as the row address, “Row (0) 0”indicative of the 0th row of the 0th bank is generated.

[0012] {circle over (2)} Bank Address (B) and Start Column Address (Y)

[0013] Further, the address generator continuously generates a bankaddress (CBK) specifying a bank which stores a column address after aclock cycle <2>. Here, as the bank address, “CBK (0)” specifying the 0thbank is generated.

[0014] It is to be noted that the bank address (CBK) generated togetherwith the start column address specifies the same bank (e.g., the 0thbank) as the bank specified by the bank address (RBK) generated togetherwith the row address.

[0015] Furthermore, the address generator sequentially generates a startcolumn address (Col) for each burst length in a period that the bankaddress “CBK (0)” is generated. Here, since the burst length is “2”,every other address value is generated in accordance with each two clockcycles.

[0016] That is, as the start column address, “Col (0) 0” indicative ofthe 0th column (first address) of the 0th bank is generated in thecycles <2>and <3>. Subsequently, “Col (0) 2” indicative of the secondcolumn as a next first address is generated in the cycles <4>and <5>.Then, “Col (0) 4” indicative of the fourth column is generated in thecycles <6>and <7>. In this manner, the start column addresses arethereafter sequentially generated.

[0017] {circle over (3)} Increment Value (Z)

[0018] Moreover, the generated start column address is incremented inaccordance with a clock cycle. Therefore, a value (Z) to be incrementedis repeatedly generated in accordance with each cycle periodcorresponding to the burst length.

[0019] That is, “0” is generated as the increment of the first cycle<2>in the cycles <2>and <3>in which the 0th column is generated as thestart column address, and “1” is generated as the increment in the nextcycle <3>. “0” and “1” are thereafter alternately generated as theincrement for each cycle since the burst length is “2” in this manner.

[0020] (2) Input Timing to Memory Device

[0021] The row address, the row bank address, the column address and thecolumn bank address together with commands are multiplexed and inputtedto the SDRAM. That is, in addresses generated in the address generator,only an address generated at the time of inputting a command iseffective in the SDRAM.

[0022] In the example indicated by (A) in FIG. 4, the row address andthe bank address are inputted to the SDRAM together with a command “ACT”in the cycle <1>. Here, as the bank address, a bank address “RBK (0)”specifying the 0th bank is inputted. Additionally, as the row address,“Row (0) 0” indicative of the 0th row of the 0th bank is inputted.

[0023] It is to be noted that the command “ACT” instructs activation ofa target bank of the SDRAM, and also instructs input of the row addressto that bank.

[0024] Subsequently, in the cycle <2>, the start column address and thebank address are inputted to the SDRAM together with a command “READ”.Here, as the bank address, a bank address “CBK (0)” specifying the 0thbank is inputted. Further, as the start column address, “Col (0)”indicative of the 0th column of the 0th bank is inputted.

[0025] This command “READ” instructs reading from a corresponding memorycell of the SDRAM. Therefore, in the cycle <2>, information in thememory cell at the 0th row (Row (0) 0) and the 0th column (Col (0) 0) ofthe 0th bank (BK (0)) is read.

[0026] It is to be noted that information is written in a correspondingmemory cell when a command “WRITE” is inputted in place of the command“READ”.

[0027] The SDRAM has a burst function with respect to thecolumn-addresses. That is, in the memory device, the start columnaddress is automatically incremented for each clock cycle, and thecolumn address is then sequentially generated.

[0028] Therefore, in the cycle <3>, the start column address isincremented in the memory address, and a column address “Col (0) 1”indicative of the first column is generated. Accordingly, in the cycle<3>in the burst operation, information of a next cell is outputted as aresponse output from the memory address even if the command “READ” orthe column address is not inputted.

[0029] In this conventional example, since the burst length is “2”, thecommand “READ”, the next start column address and the bank address “CBK(0)” are thereafter inputted every other cycle. That is, theeven-numbered start column addresses “Col (0) 2”, “Col (0) 4”, “Col (0)6”, . . . are sequentially inputted in even-numbered cycles <4>, <6>,<8>. . .

[0030] Therefore, in the odd-numbered cycles <3>, <5>, <7>, . . . ,commands and the like are not inputted from the test pattern generatorto the SDRAM at all.

[0031] (3) Input Timing to Failure Analysis Memory

[0032] {circle over (1)} Row Address (X) and Bank Address (N) Therefore,in the example indicated by (C) in FIG. 4, after the cycle <1>, the bankaddress “RBK (0)” specifying the 0th bank and the row address “Row (0)0” indicative of the 0th row of the 0th bank are continuously inputted.These bank address and row address are the same as those generated inthe command generator.

[0033] (2) Column Address (Y+Z) and bank address (B) Furthermore, afterthe cycle. <2>, the bank address “CBK (0)” specifying the 0th bank iscontinuously inputted.

[0034] Then, in each cycle after the cycle <2>, a column addressobtained by adding an increment value (Z) to the start column address(Y) generated in the address generator is inputted to the failureanalysis memory. That is, in the cycles <2>, <3>, <4>, . . . , thecolumn addresses “Col (0) 0”, “Col (0) 1”, “Col (0) 2”, . . . aresequentially inputted. As a result, the same address space as that inthe SDRAM can be set in the failure analysis memory.

[0035] After the test with respect to each memory cell in the 0th bankis completed in this manner, each memory cell in the next first bank istested. In case of testing the first bank, the test of the same timingas that of addresses and the like in the 0th bank is carried out exceptthat an address specifying the first bank is determined as the bankaddress. Thereafter, the remaining banks are likewise sequentiallytested in the same manner.

[0036] Meanwhile, in the memory device, a memory area is divided into aplurality of banks, and an inter-bank interleave operation toalternately perform reading/writing with respect to these banks may beperformed. Carrying out the inter-bank interleave operation can increasean access speed to the memory.

[0037] When the memory device is operated in the inter-bank interleavemode, in the memory device, a row address is given in accordance witheach bank in advance by the command “ACT”, and reading/writing of a cellcorresponding to a column address of a specified bank together with thecommand “READ” or “WRITE”.

[0038] However, in the failure analysis memory, fail information isstored at an address corresponding to a row address and its bankinputted when a column address and its bank are specified. Therefore, inthe failure analysis memory, when the column address and the bank ofthat column address are specified, the same bank as that bank and a rowaddress of that bank must be simultaneously specified. In the failureanalysis memory, the same address space as that in the memory deviceunder test must be set.

[0039] Therefore, in the conventional semiconductor memory testapparatus, the memory device having the burst function is hard togenerate an address which is inputted to the failure analysis memoryused to test the inter-bank interleave operation.

[0040] Accordingly, in view of the above-described problems, it is anobject of the present invention to provide a semiconductor memory testapparatus and a failure analysis address generator by which a memorydevice having a burst function can readily generate an address which isinputted to a failure analysis memory used to test an inter-bankinterleave operation.

DISCLOSURE OF THE INVENTION

[0041] According to the present invention, there is provided asemiconductor memory test apparatus which determines as a device undertest a memory device whose memory area is constituted by a plurality ofbanks and operates in a burst mode with respect to column addresses (orrow addresses), comprising: a test pattern generator which generates atest pattern signal and a expected value pattern signal; a logiccomparator which compares a response output signal of the memory deviceunder test having the test pattern signal inputted thereto with theexpected value pattern signal, and detects a mismatch as a failure cell;and a failure analysis memory which stores failure information at thesame address as an address in the memory device of the failure cell, thesemiconductor memory test apparatus further comprising a failureanalysis address generator which generates a failure analysis addressused to set in the failure analysis memory the same address space asthat in the memory device in the burst mode operation, wherein thefailure analysis address generator has a register file block having aregister corresponding to each bank of the memory device, holds a rowaddress (or a column address) of a corresponding bank in each register,reads a row address (or a column address) of the same bank as a startcolumn address (or a start row address) from a register corresponding toany bank when the start column address (or the start row address) ofthat bank is inputted to the memory device, outputs it to the failureanalysis memory together with the start column address (or the start rowaddress), and outputs to the failure analysis memory the row address (orthe column address) together with the same column address (or rowaddress) as that in the memory device generated by calculating the startcolumn address (or the start row address) in accordance with each clockcycle.

[0042] According to such a present invention, the row address (or thecolumn address) held in the register can be inputted to the failureanalysis memory, and that row address can be inputted to the failureanalysis memory with an arbitrary timing in a period of holding that rowaddress without being restricted to a generation timing of that rowaddress. As a result, the same address space as that in the memorydevice which is performing the inter-bank interleave operation in theburst mode can be readily set in the failure analysis memory.

BRIEF DESCRIPTION OF THE DRAWINGS

[0043]FIG. 1 is a block diagram illustrating an outline of a preferredembodiment of a semiconductor memory test apparatus according to thepresent invention;

[0044]FIG. 2 is a block diagram illustrating a structure of thepreferred embodiment of the semiconductor memory test apparatus and afailure analysis address generator according to the present invention;

[0045]FIG. 3 is a timing chart illustrating an operation of thepreferred embodiment of the semiconductor memory test apparatus and thefailure analysis address generator according to the present invention;and

[0046]FIG. 4 is a timing chart illustrating an operation of aconventional semiconductor test apparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

[0047] In order to explain the present invention in further detail, anembodiment of a semiconductor test apparatus and a failure analysisaddress generator according to the present invention will now bedescribed hereinafter with reference to the accompanying drawings.

1. Structure

[0048] First, a description will be given as to a structure of thesemiconductor memory test apparatus and the failure analysis memorygenerator according to the embodiment with reference to FIGS. 1 and 2.

[0049] In this embodiment, as a memory device 5, an SDRAM is determinedas a device under test. This SDRAM has a memory area constituted by fourbanks, and performs a burst mode operation with a burst length of “2”with respect to column addresses.

[0050] As shown in FIG. 1, the semiconductor memory test apparatusaccording to this embodiment includes a test pattern generator 1, alogic comparison circuit 2, a failure analysis memory 3, and a failureanalysis address generator 4.

[0051] It is to be noted that illustrations and explanations of a timinggenerator, a delay circuit, a pin electronics and the like included in aregular semiconductor memory test apparatus are omitted in thisembodiment.

[0052] The test pattern generator 1 generates a test pattern signal andan expected pattern signal. Therefore, the test pattern generator 1 isconstituted by a command generator 11, an address generator 12, a testpattern signal generation block 13, and an expected value pattern signalgeneration block 14.

[0053] The command generator 11 generates a command “ACT” and a command“READ” or “WRITE”. The command “ACT” is generated every two cycleperiods corresponding to the burst length. Further, the command “READ”or “WRITE” is generated every two cycle periods corresponding to theburst length in a cycle that the command “ACT” is not generated.

[0054] The address generator 12 sequentially generates a bank address(N) and a row address X every two cycle periods corresponding to theburst length of the memory device with respect to each bank.

[0055] It is to be noted that the bank address (N) specifies any bank inthe four banks of the memory device 5, and the row address (X) isindicative of a row address in the specified bank.

[0056] Furthermore, the address generator 12 sequentially generates abank address (B) and a start column address Y every two cycle periodscorresponding to the burst length with respect to each bank.

[0057] It is to be noted that the bank address (B) specifies any one inthe four banks of the memory device 5. Moreover, the bank specified bythis bank address (B) may be any bank whose bank address (N) isspecified.

[0058] Additionally, the start column address is a top column address ofthe burst and takes a non-continuous value for each burst length. Here,since the burst length is “2”, the start column address is every othervalue.

[0059] Further, the address generator 12 generates a column address byincrementing a start column address for each clock cycle in the burstoperation of the bank. Here, every time the start column address isgenerated, an increment value Z which is increased for each clock cycleis generated, and a column address (Y+Z) obtained by adding theincrement value Z to the start column address (Y) is generated.

[0060] As a result, the column address corresponding to the columnaddress automatically generated in the memory device 5 in the burstoperation can be generated. Here, since the burst length is “2”, thecolumn address obtained by incrementing the start column address by “+1”is generated in a next clock cycle after the start column address isproduced.

[0061] It is to be noted that the increment processing may be carriedout outside the address generator 12.

[0062] Furthermore, the test pattern signal generation block 13generates test pattern signal by combining a command issued in thecommand generator 11 with an address produced in the address generator12.

[0063] That is, when the command “ACT” is generated, the test patternsignal generation block 13 combines that command with the row address(X), and outputs a result to the memory device 5. Moreover, when thecommand “READ” or “WRITE” is generated, the test pattern signalgeneration block 13 combines that command with the start column address,and outputs a result to the memory device 5.

[0064] Additionally, the test pattern signal is inputted to the memorydevice 5 as a device under test (DUT). Further, an expected valuepattern signal generated in the expected value pattern signal generationblock 14 is inputted to the logic comparison circuit 2.

[0065] Furthermore, the logic comparison circuit 2 compares a responseoutput signal of the memory device 5 having the test pattern signalinputted thereto with the expected value pattern signal. Moreover, itdetects a result of mismatch as a failure cell. When the failure cell isdetected, failure information is supplied to the failure analysis memory3.

[0066] The failure analysis memory 3 stores the failure information atthe same address as an address in the memory device of the failure cell.

[0067] Additionally, the failure analysis address generator 4 generatesa failure analysis address used set in the failure analysis memory thesame address space as that in the memory device 5 which is performingthe burst mode operation.

[0068] Therefore, the failure analysis address generator 4 provides aregister corresponding to each bank of the memory device, and holds therow address of a corresponding bank in each register. Further, when thestart column address (Y) of any bank is inputted to the memory device 5,the row address of the same bank as that of the start column address (Y)is read from the register corresponding to that bank. Subsequently, theread row address is outputted to the failure analysis memory 3 togetherwith the start column address. Furthermore, in the burst operation ofthe bank, the column address is generated by operating that start columnaddress for each clock cycle, and that row address is outputted to thefailure analysis memory 3 together with the generated column address.

[0069] A structure of the failure analysis address generator 4 will nowbe described in detail with reference to FIG. 2.

[0070] It is to be noted that FIG. 2 shows only the address generator 12in the test pattern generator 1 depicted in FIG. 1 and omits any otherconstituent element. Moreover, the illustration of the logic comparisoncircuit 2 in FIG. 1 is also omitted.

[0071] The failure analysis address generator 4 is constituted by aregister file block 40, a write register selection block 41, a readregister selection block 42, an address control block 43 and a rowaddress selection block 44.

[0072] The write register selection block 41 selects a register of theregister file block 40 in which a row address (X) is written inaccordance with a bank address (N) outputted together with the rowaddress (X).

[0073] Additionally, the read register selection portion 42 selects aregister used to read a row address REX stored in the register fileblock 40 in accordance with a bank address (B) outputted together with acolumn address (Y+Z).

[0074] Further, the address control block 43 generates a writeinstruction signal (RFWT) when the row address (X) of any bank isinputted from the test pattern generator 1 to the memory device 5.Furthermore, when a start column address (Y) of any bank is inputted tothe memory device 5, the address control block 43 generates a readinstruction signal (RFRD) in the burst operation of the bank having thestart address (Y) inputted thereto.

[0075] Moreover, the register file block 40 has 0th to third registers400 to 403 respectively corresponding to 0th to third banks 50 to 53 ofthe memory device. Additionally, when the write instruction signal(RFWT) is generated from the address control block 43, the register fileblock 40 writes the row address in a register selected by the writeregister selection block 41.

[0076] When the read instruction signal (RFRD) is generated from theaddress control block 43, the row address selection block 44 reads therow address from a register selected by the read register selectionblock 42, and outputs is to the failure analysis memory. Further, whenthe read instruction signal (RFRD) is not generated, the row addressselection block 44 outputs the row address (X) generated in the addressgenerator 12 to the failure analysis memory as it is.

[0077] It is to be noted that the column address (Y+Z) generated in theaddress generator 12 is inputted to the failure analysis memory 3 as itis.

2. Operation

[0078] An operation of the semiconductor memory test apparatus accordingto the embodiment will now be described with reference to a timing chartof FIG. 3.

[0079] Here, there is illustrated an example of an address generationtiming when testing the SDRAM which has four banks, operates in theburst mode with respect to column addresses and has the burst length of“2”.

[0080] (A) in FIG. 3 indicates input timings of a command, an addressand a bank address to the memory device as a device under test (DUT).Furthermore, (B) in FIG. 3 indicates generation timings of a rowaddress, a start column address, an increment value and a bank addressin the address generator of the test pattern generator (ALPG). Moreover,(B) in FIG. 3 also indicates generation timings of a write instructionsignal (RFWT) and a read instruction signal (RFRD).

[0081] Additionally, (C) in FIG. 3 indicates a timing that a row addressis stored and held in each register of the register file block 40.Further, (D) in FIG. 3 indicates input timings of a row address and acolumn address as failure analysis addresses to the failure analysismemory (FM).

[0082] A description will now be given as to (1) generation timings ofaddresses and the like in the test pattern generator indicated by (B) inFIG. 3, (2) input timings of addresses and the like to the memory deviceindicated by (A) in FIG. 3, (3) storage timings or the like of a rowaddress in the register file block indicated by (C) in FIG. 3, (4) inputtimings of addresses and the like to the failure analysis memoryindicated by (D) in FIG. 3, and (5) the operation for each cycle in thementioned order.

[0083] (1) Generation Timing in Test Pattern Generator

[0084] {circle over (1)} Row address (X) and bank address (N)

[0085] As indicated by (B) in FIG. 3, the address generator 12sequentially generates a bank address (N) and a row address (X) withrespect to each bank in accordance with each cycle period correspondingto the burst length of the memory device. Here, since the burst lengthis “2”, the bank address (N) and the row address (X) are generated everytwo clock cycles.

[0086] That is, as indicated by (B) in FIG. 3, in the cycles <1>and <2>,the bank address “RBK (0)” specifying the 0th bank is generated togetherwith the row address “Row (0) 0” indicative of the 0th row of the 0thbank. Subsequently, in the cycles <3>and <4>, the bank address “RBK (1)”specifying the first bank is generated together with the row address“Row (1) 0” indicative of the 0th row of the first bank.

[0087] Thereafter, the bank addresses and the row addresses with respectto the second bank and the third bank are generated every two cycles inthe similar manner. Further, after all the banks are specified, apattern to sequentially specify from the 0th bank is again repeated. Atthat time, values of the row addresses are sequentially calculated everytime all of the respective banks are specified.

[0088] For example, as indicated by (B) in FIG. 3, in the cycles <9>and<10>, the bank address “RBK (0)” specifying the 0th bank is generatedtogether with “Row (0) 1” indicative of the first row of the 0th bank.Likewise, although not shown, the bank address “RBK (0)” specifying the0th bank is generated together with “Row (0) 2” indicative of the secondrow of the 0th bank in the cycles <17>and <18>.

[0089] {circle over (2)} Bank Address (B) and Start Column Address (Y)

[0090] The address generator 12 sequentially generates the bank address(B) and the start column address (Y) with respect to each bank inaccordance with each cycle period corresponding to the burst length inthe clock cycle <4>and subsequent clock cycles. Here, since the burstlength is “2”, the bank-address and every other start column addressvalue are generated every two clock cycles.

[0091] That is, as indicated by (B) in FIG. 3, in the cycles <4>and <5>,the bank address “CBK (0)” specifying the 0th bank is generated togetherwith the column address “Col (0) 0” indicative of the 0th column of the0th bank. Subsequently, in the cycles <6>and <7>, the bank address “CBK(1)” specifying the first bank is generated together with the columnaddress “Col (1) 0” indicative of the 0th column of the first bank.

[0092] Thereafter, the bank address (B) and the column address (X) areoutputted with respect to the second bank and the third bank every twocycles in the similar manner. At that time, since the burst length is“2”, every two column address values are calculated.

[0093] For example, although not shown, in the cycles <12>and <13>, thebank address “CBK (0)” specifying the 0th bank is generated togetherwith “Col (0) 2” indicative of the second column of the 0th bank.Further, in the cycles <20>and <21>, the bank address “CBK (0)”specifying the 0th bank is generated together with “Col (0) 4”indicative of the fourth column of the 0th bank.

[0094] {circle over (3)} Increment Value (Z)

[0095] Furthermore, the generated start column address is calculated inaccordance with each clock cycle. For the purpose, the value (Z) used incalculation is repeatedly generated in accordance with each cycle periodcorresponding to the burst length.

[0096] It is to be noted that the increment value (Z) may be generatedin the address generator 12 or it may be generated outside the addressgenerator 12.

[0097] That is, as indicated by (B) in FIG. 3, in the cycles <4>and<5>in which the 0th column is generated as the start column address, “0”is generated as an increment value of the first cycle <4>, and “1” isgenerated as an increment value in the next cycle <5>. Thereafter, sincethe burst length is “2”, “0” and “1” are alternately generated asincrement values in the similar manner.

[0098] (2) Input Timing to Memory Device

[0099] {circle over (1)} Command “ACT” and Row Address (X)

[0100] To the memory device 5 are inputted an address multiplexed with acommand by the test pattern signal generation block 13 and a bankaddress. That is, of addresses generated in the address generator, onlyan address generated at the time of inputting a command is effective inthe memory device 5 as a test pattern signal.

[0101] The command generator 11 generates a command “ACT” with anarbitrary cycle in a cycle that commands “READ” and “WRITE” are notgenerated. Here, since the burst length is “2”, the command “ACT” isgenerated every other cycle in the odd-numbered cycles <1>, <3>, <5>, .. .

[0102] Moreover, the test pattern signal generation block 13 inputs therow address (X) and the bank address (N) generated in the addressgenerator 12 at the time of generation of the command “ACT” to thememory device 5 together with the command “ACT”.

[0103] Therefore, the bank address and the row address arbitrarilyspecified with respect to each bank are inputted together with thecommand “ACT” every other cycle.

[0104] For example, as indicated by (A) in FIG. 3, in the cycle <1>, thebank address “RBK (0)” specifying the 0th bank and “Row (0) 0”indicative of the 0th row of the 0th bank are inputted together with thecommand “ACT”. Additionally, in the cycle <3>, the bank address “RBK(1)” specifying the first bank and “Row (1) 0” indicative of the 0th rowof the first bank are inputted together with the command “ACT”. Further,in the cycle <5>, the bank address “RBK (2)” specifying the second bankand “Row (2) 0” indicative of the 0th row of the second bank areinputted together with the command “ACT”.

[0105] {circle over (2)} Command “READ” and Start Column Address (Y)

[0106] Furthermore, in a cycle that the command “ACT” is not generated,the command generator 11 generates the command “READ” or “WRITE” inaccordance with each cycle period corresponding to the burst length. Inthis embodiment, since the burst length is “2”, the command “READ” isgenerated every other cycle in the even-numbered cycles 4>, <6>, <8>, .. .

[0107] It is to be noted that a description will be given as to anexample of inputting the command “READ” in this embodiment, but thecommand “WRITE” may be inputted with the similar timing.

[0108] Moreover, the test pattern signal generation block 13 inputs thestart column address (Y) and the bank address (B) generated in theaddress generator 12 at the time of generation of the command “READ” tothe memory device 5 together with the command “READ”.

[0109] It is to be noted that this command “READ” is generated in a topcycle that the start column address (Y) is generated in the addressgenerator 12.

[0110] Therefore, the bank address and the start column addressspecified with respect to each bank are inputted together with thecommand “READ” every other cycle.

[0111] For example, as indicated by (A) in FIG. 3, in the cycle <4>, thebank address “CBK (0)” specifying the 0th bank and “Col (0) 0”indicative of the 0th column of the 0th bank are inputted together withthe command “READ”. Additionally, in the cycle <6>, the bank address“CBK (1)” specifying the first bank and “Col (1) 0” indicative of the0th column of the first bank are inputted together with the command“READ”. Further, in the cycle <8>, the bank address “CBK (2)” specifyingthe second bank and “Col (2) 0” indicative of the 0th column of thesecond bank are inputted together with the command “READ”.

[0112] By alternately inputting the command “ACT” and the command “READ”with such timings, a row address of another bank can be inputted to thememory device when one bank of the memory device is performing the burstoperation.

[0113] (3) Storage Timing and Others of Row Address in Register FileBlock

[0114] The register file block 40 writes the row address (X) in aregister selected by the write register selection block when a writeinstruction signal “RFWT” is generated. That is, when the row address(X) of any bank is inputted from the test pattern generator to thememory device 5 together with the command “ACT”, the register file block40 stores that row address (X) in a register corresponding to that bank.

[0115] For example, as indicated by (C) in FIG. 3, in the cycle <1>, therow address “Row (0) 0” indicative of the 0th row of the 0th bank isstored in a 0th register 400. Furthermore, in the cycle <3>, “Row (1) 0”indicative of the 0th row of the first bank is stored in a firstregister 401. Moreover, in the cycle <5>, “Row (2) 0” indicative of the0th row of the second bank is stored in a second register 402.Additionally, in the cycle <7>, “Row (3) 0” indicative of the 0th row ofthe third bank is stored at a 0th address 400;

[0116] Further, in the cycle <9>, the row address “Row (0) 1” indicativeof the first row of the 0th bank is stored in the 0th register 400. Thatis, each register holds the row address stored immediately before thenext row address is stored.

[0117] (4) Input Timing to Failure Analysis Memory

[0118] {circle over (1)} Row Address (X)

[0119] When a read instruction signal “RFRD” is generated, a row addressselection block 44 reads a row address from a register selected by aread register selection block 42, and inputs it to the failure analysismemory 3. At the time of inputting the start column address (Y) of anybank to the memory device 5, the read instruction signal “RFRD” isgenerated by an address control block 43 when that bank is performingthe burst operation. Therefore, in a period that the start columnaddress (Y) is generated, a row address (RFX) held in a registercorresponding to the bank at that start column address is read.

[0120] For example, as indicated by (D) in FIG. 3, in the cycles <4>and<5>, the row address “Row (0) 0” held in the 0th register 400 isinputted to the failure analysis memory 3. In the cycles <6>and <7>, therow address “Row (1) 0” held in the first register 400 is inputted tothe failure analysis memory 3. In the cycles <8>and <9>, the row address“Row (2) 0” held in the second register 402 is inputted to the failureanalysis memory 3.

[0121] {circle over (2)} Column Address (Y+Z) and Bank Address (B) Inthis embodiment, the column address (Y+Z) and the bank address (B)generated in the address generator 12 are inputted to the failureanalysis memory 3 as they are.

[0122] Furthermore, an address in the failure analysis memory 3 isspecified by a combination of the bank address, the row address and thecolumn address inputted to the failure analysis memory 3.

[0123] (5) Operation for Each Cycle

[0124] The operation illustrated in the timing chart of FIG. 3 will nowbe described in accordance with each cycle.

[0125] Cycle <1>

[0126] In the cycle <1>, the row address “Row (0) 0” and the bankaddress “RBK (0)” generated in the address generator 12 are inputted tothe memory device 5 together with the command “ACT”.

[0127] Moreover, the row address “Row (0) 0” is written in the 0thregister 400 of a register file 40 by the write instruction signal“RFWT”.

[0128] Cycle <3>

[0129] In the cycle <3>, the row address “Row (1) 0” and the bankaddress “RBK (1)” generated in the address generator 12 are inputted tothe memory device 5 together with the command “ACT”.

[0130] Additionally, the row address “Row (1) 0” is written in the firstregister 401 by the write instruction signal “RFWT”.

[0131] Cycle <4>

[0132] In the cycle <4>, the start column address “Col (0) 0” and thebank address “CBK (0)” generated in the address generator 12 areinputted to the memory device 5 together with the command “READ”.

[0133] Further, based on the read instruction signal “RFRD”, the rowaddress “Row (0) 0” held in the 0th register 400 is read and inputted tothe failure analysis memory 3. Further, the column address “Col (0) 0”generated in the address generator 12 is also inputted to the failureanalysis memory 3. As a result, a memory cell at the row address “Row(0) 0” and the column address “Col (0) 0” of the 0th bank is specified.

[0134] Cycle <5>

[0135] In the cycle <5>, the row address “Row (2) 0” and the bankaddress “RBK (2)” generated in the address generator 12 are inputted tothe memory device 5 together with the command “ACT”.

[0136] It is to be noted that the column address “Col (0) 1” followingthe start column address “Col (0) 0” is automatically generated by theburst function in the memory device 5.

[0137] Furthermore, in the cycle <5>, based on the write instructionsignal “RFWT”, the row address “Row (2) 0” is written in the secondregister 402.

[0138] Moreover, based on the read instruction signal “RFRD”, the rowaddress “Row (0) 0” held in the 0th register 400 is again read andinputted to the failure analysis memory 3. Additionally, the columnaddress “Col (0) 1” generated in the address generator 12 is alsoinputted to the failure analysis memory 3. As a result, a memory cell atthe row address “Row (0) 0” and the column. address “Col (0) 0” of the0th bank is specified.

[0139] Cycle <6>

[0140] In the cycle <6>, the start column address “Col (1) 0” and thebank address “CBK (1)” generated in the address generator 12 areinputted to the memory device 5 together with the command “READ”.

[0141] Further, based on the read instruction signal “RFRD”, the rowaddress “Row (1) 0” held in the 0th register 401 is read and inputted tothe failure analysis memory 3. Furthermore, the column address “Col (1)0” generated in the address generator 12 is also inputted to the failureanalysis memory 3. As a result, a memory cell at the row address “Row(1) 0” and the column address “Col (1) 0” of the first bank isspecified.

[0142] Cycle <7>

[0143] In the cycle <7>, the row address “Row (3) 0” and the bankaddress “RBK (3)” generated in the address generator 12 are inputted tothe memory device 5 together with the command “ACT”.

[0144] It is to be noted that the column address “Col (1) 1” followingthe start column address “Col (1) 0” is automatically generated by theburst function in the memory device 5.

[0145] Moreover, in the cycle <7>, based on the write instruction signal“RFWT”, the row address “Row (3) 0” is written in the third register403.

[0146] Further, based on the read instruction signal “RFRD”, the rowaddress “Row (1) 0” held in the first register 401 is again read andinputted to the failure analysis memory 3. Furthermore, the columnaddress “Col (1) 1” generated in the address generator 12 is alsoinputted to the failure analysis memory 3. As a result, a memory cell atthe row address “Row (1) 0” and the column address “Col (1) 1” of thefirst bank is specified.

[0147] Cycle <8>

[0148] In the cycle <8>, the start column address “Col (2) 0” and thebank address “CBK (2)” generated in the address generator 12 areinputted to the memory device 5 together with the command “READ”.

[0149] Additionally, based on the read instruction signal “RFRD”, therow address “Row (2) 0” held in the second register 402 is read andinputted to the failure analysis memory 3. Further, the column address“Col (2) 0” generated in the address generator 12 is also inputted tothe failure analysis memory 3. As a result, a memory cell at the rowaddress “Row (2) 0” and the column address “Col (2) 0” of the secondbank is specified.

[0150] Cycle <9>

[0151] In the cycle <9>, the row address “Row (0) 1” and the bankaddress “RBK (0)” generated in the address generator 12 are inputted tothe memory device 5 together with the command “ACT”.

[0152] Furthermore, the column address “Col (2) 1” following the startcolumn address “Col (2) 0” is automatically generated by the burstfunction in the memory device 5.

[0153] Moreover, in the cycle <9>, based on the write instruction signal“RFWT”, the row address “Row (0) 1” is written in the 0th register 400.

[0154] Additionally, based on the read instruction signal “RFRD”, therow address “Row (2) 0” held in the second register 401 is again readand inputted to the failure analysis memory 3. Further, the columnaddress “Col (2) 1” generated in the address generator 12 is alsoinputted to the failure analysis memory 3. As a result, a memory cell atthe row address “Row (2) 0” and the column address “Col (2) 1” of thesecond bank is specified.

[0155] Cycle <10>

[0156] In the cycle <10>, the start column address “Col (3) 0” and thebank address “CBK (3)” generated in the address generator 12 areinputted to the memory device 5 together with the command “READ”.

[0157] On the other hand, based on the read instruction signal “RFRD”,the row address “Row (3) 0” held in the third register 403 is read aninputted to the failure analysis memory 3. Furthermore, the columnaddress “Col (3) 0” generated in the address generator 12 is alsoinputted to the failure analysis memory 3. As a result, a memory cell atthe row address “Row (3) 0” and the column address “Col (3) 0” of thethird bank is specified.

[0158] Thereafter, in each of the subsequent cycles, the failureanalysis addresses are inputted to the failure analysis memory 3 in thesimilar manner.

[0159] As described above, in this embodiment, the row address (RFX)held in the register is inputted to the failure analysis memory 3.Therefore, that row address can be inputted to the failure analysismemory 3 with an arbitrary timing in a period of holding that towaddress without being restricted to a generation timing of that rowaddress.

[0160] As a result, the same address space as that in the memory deviceperforming the inter-bank interleave operation in the burst mode can bereadily set in the failure analysis memory.

[0161] It is to be noted that the description has been given as to theexample that the present invention is constituted under specificconditions in the foregoing embodiment, but the present invention can bemodified in many ways. For example, the description has been given as tothe example that the burst length is “2” in the above embodiment, butthe burst length is not restricted thereto in the present invention. Forexample, the burst length may be determined as “4” or “8”.

[0162] Moreover, although the command “ACT” is generated every othercycle in the foregoing embodiment, a generation interval of the command“ACT” is not restricted thereto in the present invention.

[0163] Additionally, although the description has been given on theexample that the failure analysis address generator is provided outsidethe test pattern generator in the above embodiment, a part or all of thefailure analysts address generator may be included in the test patterngenerator.

[0164] Further, although the description has been given as to the casethat the memory device operates with respect to the column address inthe burst mode in the foregoing embodiment, the memory device mayoperate with respect to the row address in the burst mode. In such acase, the column address (start column address) described in the aboveembodiment serves as the row address (start row address), and the rowaddress functions as the column address. Furthermore, theabove-described row address selection block 44 becomes a column addressselection block.

Industrial Applicability

[0165] As described above, the semiconductor memory test apparatusaccording to the present invention can input an address (row address)held in a register to the failure analysis memory, and that row addresscan be inputted to the failure analysis memory with an arbitrary timingin a period of holding that row address without being restricted to ageneration timing of that row address.

[0166] Therefore, the present invention is suitable for using thefailure analysis memory which stores a test result of the memory devicewhich operates in the burst mode and is performing the inter-bankinterleave operation.

1. A semiconductor memory test apparatus which tests as a device undertest a memory device whose memory area is constituted by a plurality ofbanks and which operates with respect to a column address (or a rowaddress) in a burst mode, comprising: a test pattern generator whichgenerates a text pattern signal and an expected value pattern signal; alogic comparator which compares a response output signal of the memorydevice under test having the test pattern signal inputted thereto withthe expected value pattern signal, and detects a result of a mismatch asa failure of a cell; and a failure analysis memory which stores failureinformation at the same address as an address of the failure cell in thememory device, the semiconductor memory test apparatus furthercomprising a failure analysis address generator which generates afailure analysis address used to set in the failure analysis memory thesame address space as that in the memory device which is in the burstmode operation, wherein the failure analysis address generator has aregister file block having registers corresponding to the respectivebanks of the memory device.
 2. The semiconductor memory test apparatusaccording to claim 1, wherein the register file block holds a rowaddress (or a column address) of a corresponding bank in each register,reads a row address (or a column address) of the same bank as a startcolumn address (or a start row address) of any bank and outputs it tothe failure analysis memory together with the start column address (orthe start row address) when the start column address (or the start rowaddress) is inputted to the memory device, and outputs the row address(or the column address) to the failure analysis memory together with thesame column address (or the row address) as that in the memory devicegenerated by operating the start column address (or the start rowaddress) in accordance with each clock cycle in the burst operation ofthe bank.
 3. The semiconductor memory test apparatus according to claim1 or 2, wherein, when a row address (or a column address) of any bank isinputted from the test pattern generator to the memory device, thefailure analysis address generator stores the row address (or the columnaddress) in a register corresponding to that bank.
 4. The semiconductormemory test apparatus according to claims 1 to 3, wherein the failureanalysis address generator holds in each register a row address (or acolumn address) stored immediately before a next row address (or columnaddress) is stored.
 5. The semiconductor memory test apparatus accordingto claims 1 to 4, wherein, in the burst operation of one bank of thememory device, the test pattern generator inputs a row address (or acolumn address) of another bank to the memory device.
 6. Thesemiconductor memory test apparatus according to any of claims 1 to 5,wherein the test pattern generator comprises: a command generator whicharbitrarily generates a command “ACT”, and generates a command “READ” or“WRITE” in a cycle that the command “ACT” is not generated; an addressgenerator which generates a bank address specifying any bank and a rowaddress (or a column address) of that bank in a cycle periodcorresponding to a burst length of the memory device, generates a bankaddress and a start column address (or a start row address) in that bankin the cycle period corresponding to the burst length, and generates acolumn address (or a row address) by operating the start column address(or the start row address) in accordance with each clock cycle in theburst operation of that bank; and a test pattern signal generation blockwhich combines the command “ACT” with the row address (or the columnaddress) generated by the address generator at the time of generation ofthe command “ACT” and outputs a result to the memory device, andcombines the command “READ” or “WRITE” with the start column address (orthe start row address) generated by the address generator at the time ofgeneration of the command “READ” or “WRITE” and outputs a result to thememory device.
 7. The semiconductor memory test apparatus according toany of claims 1 to 6, wherein the failure analysis address generatorcomprises: a write register selection block which selects a register inwhich the row address (or the column address) is written in accordancewith a bank address which is outputted together with the row address (orthe column address) and specifies any one of the banks; and a readregister selection block which selects a register from which the-rowaddress (or the column address) is read in accordance with a bankaddress outputted together with the row address (or the column address).8. The semiconductor memory test apparatus according to claim 7, whereinthe failure analysis address generator has: an address control blockwhich generates a write instruction signal when a row address (or acolumn address) of any bank is inputted from the test pattern generatorto the memory device, and generates a read instruction signal when astart column address (or a start row address) of any bank is inputted tothe memory device and that bank is performing the burst operation: and arow address (or column address) selection block which reads a rowaddress (or a column address) from a register selected by the readregister selection block and outputs it to the failure analysis memory,wherein the register file block writes a row address (or a columnaddress) in a register selected by the write register selection blockwhen the write instruction signal is generated.
 9. The semiconductormemory test apparatus according to claim 8, wherein the row address (orcolumn address) selection block outputs a row address (or a columnaddress) generated in the address generator to the failure analysismemory when the read instruction signal is not generated.
 10. Thesemiconductor memory test apparatus according to any of claims 1 to 9,wherein the memory device is an SDRAM (synchronous DRAM).
 11. A methodfor address generation for failure analysis which generates a failureanalysis address used to set in a failure analysis memory the sameaddress space as that in a memory device which is in a burst modeoperation in a semiconductor memory test apparatus which tests as adevice under test the memory device whose memory area is constituted bya plurality of banks and which operates with respect to a column address(or a row address) in a burst mode, the method comprising: a step ofholding a row address (or a column address) of a corresponding bank ineach register of a register file block having registers corresponding tothe respective banks of the memory device; a step of reading a rowaddress (or a column address) of the same bank as a start column address(or a start row address) of any bank from a register corresponding tothe bank and outputting it to the failure analysis memory together withthe start column address (or the start row address) when the startcolumn address (or the start row address) is inputted to the memorydevice; and a step of outputting the row address (or the column address)to the failure analysis memory together with the same column address (orthe row address) as that in the memory device generated by operating thestart column address (or the start row address) in accordance with eachclock cycle in the burst operation of the bank.